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r10ds0051ej0100 rev.1.00 page 1 of 14 2011.03.30 r1lv0216bsb 2mb advanced lpsram (128k word x 16bit) description the r1lv0216bsb is a family of low voltage 2-mbit static rams organized as 131,072-word by 16-bit, fabricated by renesas?s high-performance 0.15um cmos and tft technologies. the r1lv0216bsb has realized higher density, higher performance and low power consumption. the r1lv0216bsb is suitable for memory applications where a simple interfacing, battery operating and battery backup are the important design objectives. the r1lv0216bsb has been packaged in 44-pin tsop. features ? single 2.7~3.6v power supply ? small stand-by current: 1a (3.0v, typical) ? no clocks, no refresh ? all inputs and outputs are ttl compatible. ? easy memory expansion by cs#, lb# and ub# ? common data i/o ? three-state outputs: or-tie capability ? oe# prevents data contention on the i/o bus ordering information orderable part name access time temperature range package shipping container quantity r1lv0216bsb-5sr#b0 0 ~ +70c r1lv0216bsb-5si#b0 55 ns -40 ~ +85c r1lv0216bsb-7sr#b0 0 ~ +70c r1lv0216bsb-7si#b0 70 ns -40 ~ +85c tray max. 135pcs/tray max. 1080pcs/inner box r1lv0216bsb-5sr#s0 0 ~ +70c r1lv0216bsb-5si#s0 55 ns -40 ~ +85c r1lv0216bsb-7sr#s0 0 ~ +70c r1lv0216bsb-7si#s0 70 ns -40 ~ +85c 400-mil 44pin plastic tsop (ii) (normal-bend type) ptsb0044gd-b (44p3f-b) embossed tape 1000pcs/reel r10ds0051ej0100 rev.1.00 2011.03.30
r1lv0216bsb r10ds0051ej0100 rev.1.00 page 2 of 14 2011.03.30 pin arrangement pin description pin name function vcc power supply vss ground a0 to a16 address input dq0 to dq15 data input/output cs# chip select 1 we# write enable oe# output enable lb# lower byte enable ub# upper byte enalbe nc non connection a4 a3 a2 a1 a0 cs# dq0 dq1 dq2 dq3 vcc gnd dq4 dq5 dq6 dq7 we# a16 a15 a14 a13 a12 a 5 a6 a7 oe# ub# lb# dq15 dq14 dq13 dq12 gnd vcc dq11 dq10 dq9 dq8 nc a8 a9 a10 a11 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 44-pin tsop (ii)
r1lv0216bsb r10ds0051ej0100 rev.1.00 page 3 of 14 2011.03.30 block diagram a 0 cs# a 1 lb# ub# we# oe# a 16 dq0 dq1 dq7 dq8 dq9 dq15 vcc vss column decoder upper or lower byte control dq buffer address buffer row decoder dq buffer dat a selector sense / write amplifier clock generator memory array 128k-word x16-bit
r1lv0216bsb r10ds0051ej0100 rev.1.00 page 4 of 14 2011.03.30 operation table cs# lb# ub# we# oe# dq0~7 dq8~15 operation h x x x x high-z high-z stand-by x h h x x high-z high-z stand-by l l h l x din high-z write in lower byte l l h h l dout high-z read in lower byte l l h h h high-z high-z output disable l h l l x high-z din write in upper byte l h l h l high-z dout read in upper byte l h l h h high-z high-z output disable l l l l x din din word write l l l h l dout dout word read l l l h h high-z high-z output disable note 1. h: v ih l:v il x: v ih or v il absolute maximum parameter symbol value unit power supply voltage relative to vss vcc -0.5 to +4.6 v terminal voltage on any pin relative to vss v t -0.5 *1 to vcc+0.5 *2 v power dissipation p t 0.7 w r ver. 0 to +70 operation temperature topr *3 i ver. -40 to +85 c storage temperature range tstg -65 to 150 c r ver. 0 to +70 storage temperature range under bias tbias *3 i ver. -40 to +85 c note 1. ?3.0v for pulse 30ns (full width at half maximum) 2. maximum voltage is +4.6v. 3. ambient temperature range depends on r/i-version. please see table on page 1.
r1lv0216bsb r10ds0051ej0100 rev.1.00 page 5 of 14 2011.03.30 dc operating conditions parameter symbol min. typ. max. unit note vcc 2.7 3.0 3.6 v supply voltage vss 0 0 0 v input high voltage v ih 2.2 - vcc+0.3 v input low voltage v il -0.3 - 0.6 v 1 r ver. 0 - +70 c 2 ambient temperature range i ver. ta -40 - +85 c 2 note 1. ?3.0v for pulse 30ns (full width at half maximum) 2. ambient temperature range depends on r/i-version. please see table on page 1. dc characteristics parameter symbol min. typ. max. unit test conditions input leakage current | i li | - - 1 a vin = vss to vcc output leakage current | i lo | - - 1 a cs# = lb# = ub# = v ih or oe# =v ih , v i/o =vss to vcc i cc1 - 15 25 ma min. cycle, duty =100%, i i/o = 0ma cs# =v il , others = v ih /v il average operating current i cc2 - 2 5 ma cycle =1 s, duty =100%, i i/o = 0ma cs# 0.2v, v ih vcc-0.2v, v il 0.2v standby current i sb - - 0.5 ma (1) cs# = v ih , others =v ih /v il or (2) lb# = ub# = v ih , others =v ih /v il - 1 *1 2 a ~+25c - - 3 a ~+40c - - 8 a ~+70c standby current i sb1 - - 10 a ~+85c vin = vss to vcc (1) cs# vcc-0.2v or (2) lb# = ub# vcc-0.2v, cs# 0.2v v oh 2.4 - - v i oh = -0.5ma output high voltage v oh2 vcc - 0.5 - - v i oh = -0.05ma output low voltage v ol - - 0.4 v i ol = 2ma note 1. typical parameter indicates the value for the center of distribution at 3.0v (t a= 25oc), and not 100% tested.
r1lv0216bsb r10ds0051ej0100 rev.1.00 page 6 of 14 2011.03.30 capacitance (vcc = 2.7v ~ 3.6v, f = 1mhz, ta = 0 ~ +70c / -40 ~ +85c *2 ) parameter symbol min. typ. max. unit test conditions note input capacitance c in - - 8 pf vin =0v 1 input / output capacitance c i/o - - 10 pf v i/o =0v 1 note 1. this parameter is sampled and not 100% tested. 2. ambient temperature range depends on r/i-version. please see table on page 1. ac characteristics test conditions (vcc = 2.7v ~ 3.6v, ta = 0 ~ +70c / -40 ~ +85c *1 ) ? input pulse levels: vi l = 0.4v, vih = 2.4v ? input rise and fall time: 5ns ? input and output timing reference level: 1.5v ? output load: see figures (including scope and jig) note 1. ambient temperature range depends on r/i-version. please see table on page 1. dq 1.5v r l = 500 ohm c l = 30 pf
r1lv0216bsb r10ds0051ej0100 rev.1.00 page 7 of 14 2011.03.30 read cycle r1lv0216bsb-5s* r1lv0216bsb-7s* parameter symbol min. max. min. max. unit note read cycle time t rc 55 - 70 - ns address access time t aa - 55 - 70 ns chip select access time t acs - 55 - 70 ns output enable to output valid t oe - 30 - 35 ns output hold from address change t oh 10 - 10 - ns lb#, ub# access time t ba - 55 - 70 ns chip select to output in low-z t clz 10 - 10 - ns 2,3 lb#, ub# enable to low-z t blz 10 - 10 - ns 2,3 output enable to output in low-z t olz 5 - 5 - ns 2,3 chip deselect to output in high-z t chz 0 20 0 25 ns 1,2,3 lb#, ub# disable to high-z t bhz 0 20 0 25 ns 1,2,3 output disable to output in high-z t ohz 0 20 0 25 ns 1,2,3
r1lv0216bsb r10ds0051ej0100 rev.1.00 page 8 of 14 2011.03.30 write cycle r1lv0216bsb-5s* r1lv0216bsb-7s* parameter symbol min. max. min. max. unit note write cycle time t wc 55 - 70 - ns address valid to end of write t aw 50 - 55 - ns chip select to end of write t cw 50 - 55 - ns 5 write pulse width t wp 45 - 50 - ns 4 lb#, ub# valid to end of write t bw 50 - 55 - ns address setup time t as 0 - 0 - ns 6 write recovery time t wr 0 - 0 - ns 7 data to write time overlap t dw 25 - 30 - ns data hold from write time t dh 0 - 0 - ns output enable from end of write t ow 5 - 5 - ns 2 output disable to output in high-z t ohz 0 20 0 25 ns 1,2 write to output in high-z t whz 0 20 0 25 ns 1,2 note 1. t chz , t ohz and t whz are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. this parameter is sampled and not 100% tested. 3. at any given temperat ure and voltage condition, t hz max is less than t lz min both for a given device and from device to device. 4. a write occurs during the overlap of a low cs#, a low we# and a low lb# or a low ub#. a write begins at the latest transit ion among cs# going low, we# going low and lb# going low or ub# going low. a write ends at the earliest transition among cs# go ing high, we# going high and lb# going high or ub# going high. t wp is measured from the beginning of write to the end of write. 5. t cw is measured from the later of cs# going low to end of write. 6. t as is measured the address valid to the beginning of write. 7. t wr is measured from the earliest of cs#, we#, lb# or ub# going high to the end of write cycle. 8. don?t apply inverted phase signal ex ternally when dq pin is output mode.
r1lv0216bsb r10ds0051ej0100 rev.1.00 page 9 of 14 2011.03.30 timing waveforms read cycle t aa cs# a 0~16 t oh t clz t acs t oe t olz t chz oe# we# dq 0~15 v ih t ohz high impedance we# = ?h? level t rc valid data t blz t bhz lb#,ub# t ba
r1lv0216bsb r10ds0051ej0100 rev.1.00 page 10 of 14 2011.03.30 write cycle (1) (we# clock) cs# t cw t ow t wc dq 0~15 t dw t dh valid data t ohz oe# we# t aw t as t wp t wr t whz t olz a 0~16 lb#,ub# t bw
r1lv0216bsb r10ds0051ej0100 rev.1.00 page 11 of 14 2011.03.30 write cycle (2) (cs1#, cs2 clock) cs# a 0~16 t cw t wc t aw t as t wr oe# we# dq 0~15 v ih oe# = ?h? level t dw t dh t wp valid data lb#,ub# t bw
r1lv0216bsb r10ds0051ej0100 rev.1.00 page 12 of 14 2011.03.30 write cycle (3) (lb#, ub# clock) lb#,ub# a 0~16 t bw t wc t aw t as t wr oe# we# dq 0~15 v ih oe# = ?h? level t dw t dh t wp valid data cs# t cw
r1lv0216bsb r10ds0051ej0100 rev.1.00 page 13 of 14 2011.03.30 low vcc data retention characteristics parameter symbol min. typ. max. unit test conditions *2 v cc for data retention v dr 2.0 - 3.6 v vin 0v (1) cs# vcc-0.2v or (2) lb# = ub# vcc-0.2v, cs# 0.2v - 1 *1 2 a ~+25c - - 3 a ~+40c - - 8 a ~+70c data retention current i ccdr - - 10 a ~+85c vcc=3.0v, vin 0v (1) cs# vcc-0.2v or (2) lb# = ub# vcc-0.2v, cs# 0.2v chip deselect to data retention time t cdr 0 - - ns operation recovery time t r 5 - - ms see retention waveform. note 1. typical parameter indicates the value for the center of distribution at 3.0v (t a= 25oc), and not 100% tested. 2. cs# controls address buffer, we# buffer, oe# buffer, lb# buffer, ub# buffer and din buffer. if cs# controls data retention mode, vin levels (addr ess, we#, oe#, lb#, ub#, dq) c an be in the high impedance state.
r1lv0216bsb r10ds0051ej0100 rev.1.00 page 14 of 14 2011.03.30 low vcc data retention timing waveforms cs# vcc (1) cs# controlled t cdr t r 2.7v 2.7v 2.2v 2.2v v dr cs# vcc - 0.2v lb#, ub# vcc (2) lb#, ub# controlled t cdr t r 2.7v 2.7v 2.2v 2.2v v dr lb# , ub# vcc - 0.2v
all trademarks and registered trademarks are t he property of their respective owners. revision history r1lv0216bsb data sheet description rev. date page summary 1.00 2011.03.30 - first edition issued
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